1. Technical Field
The present invention relates generally to a semiconductor device, and more particularly, to a data output circuit of a semiconductor device.
2. Related Art
After receiving a read command, a semiconductor device, e.g. a semiconductor memory device, transmits data stored in a corresponding memory cell to a pipe latch through a path, such as a global line GIO or the like.
The pipe latch receives and arranges the transmitted data in response to a control signal PINB, thereby generating output data.
A predetermined timing margin must be secured between the transmitted data and an input control signal in order to achieve stable data output.
FIG. 1 is a schematic block diagram illustrating the configuration of a conventional data output circuit 1 of a semiconductor device.
As illustrated in FIG. 1, the conventional data output circuit 1 of a semiconductor device includes a signal generation block 10, a read data path block 20, and a control signal path block 30.
The signal generation block 10 includes a plurality of delays DLY0 to DLY2.
When a write flag signal WTS is inactivated in a read operation for example, the signal generation block 10 delays a bank selection signal AYP to generate a switching signal IOSTBP, a global line enable signal GIOEN, and a source signal PINSTB0.
The write flag signal WTS is a signal which stays in an active state (e.g. a high level) when a write operation is performed.
The bank selection signal AYP is a signal including bank address information.
The read data path block 20 includes a global line GIO, a plurality of drivers 21, and a pipe latch 23.
The plurality of drivers 21 drives and transmits data stored in a memory cell (not shown) to the global line GIO through data lines LIO, LIOB, and BIO in response to the switching signal IOSTBP and the global line enable signal GIOEN.
The pipe latch 23 receives and arranges data (hereinafter, referred to as “GIO data”), which is transmitted through the global line GIO, in response to a control signal PINB<0:k>, and then generates read data DO in response to a signal POUT<0:k>.
The read data DO is outputted to a pad DQ (not shown) through an output driver (not shown).
The control signal path block 30 includes a combination unit 31, a delay unit 32, a pulse width adjustment unit 33, and a signal generation unit 34.
The combination unit 31 combines and outputs the source signal PINSTB0 and source signals PINSTB1 to PINSTBi, which are outputted from another memory bank.
The delay unit 32 adjusts the delay time of the output signal of the combination unit 31 by a preset time according to a test mode, an option, or the like, and outputs the adjusted signal.
The pulse width adjustment unit 33 adjusts the pulse width of the output signal of the delay unit 32 by a preset value according to a test mode, an option, or the like, and outputs the adjusted signal.
The signal generation unit 34 receives the output signal of the pulse width adjustment unit 33, and generates a control signal PINB<0:k>.
According to the aforementioned conventional technique, the GIO data and the source signal PINSTB0 are generated in the same memory bank in a normal operation.
Therefore, a GIO-vs-PIN margin, which is a timing margin between the GIO data and the source signal PINSTB0, must be constant.
However, since the GIO data and the source signal PINSTB0 pass through a long RC line and a multistage logic circuit block, a variation timing margin depending on process, voltage, and/or temperature (PVT) may vary.
Additionally, a great number of parallel lines are used in the GIO data, so physical/electrical margin variables, such as a coupling effect and the like, further exist.
Since the GIO-vs-PIN margin (hereinafter, referred to as a “margin”) shows timing differences between a simulation and an actually implemented circuit, it is difficult for a designer to select an appropriate margin.
When a large margin is set for the stability of an operation, the characteristics of asynchronous parameters, such as an address access time (tAA), are deteriorated. When a small margin is set for improvement of the tAA characteristic, an operation fail may result.